\doxysubsubsubsection{DMA FIFO direct mode }
\hypertarget{group___d_m_a___f_i_f_o__direct__mode}{}\label{group___d_m_a___f_i_f_o__direct__mode}\index{DMA FIFO direct mode@{DMA FIFO direct mode}}


DMA FIFO direct mode.  


\doxysubsubsubsubsubsection*{Macros}
\begin{DoxyCompactItemize}
\item 
\#define \mbox{\hyperlink{group___d_m_a___f_i_f_o__direct__mode_gaec22b199f9da9214bf908d7edbcd83e8}{DMA\+\_\+\+FIFOMODE\+\_\+\+DISABLE}}~((uint32\+\_\+t)0x00000000U)
\item 
\#define \mbox{\hyperlink{group___d_m_a___f_i_f_o__direct__mode_ga18709570bed6b9112520701c482fbe4b}{DMA\+\_\+\+FIFOMODE\+\_\+\+ENABLE}}~((uint32\+\_\+t)\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga89406bb954742665691c0ac2f8d95ec9}{DMA\+\_\+\+Sx\+FCR\+\_\+\+DMDIS}})
\end{DoxyCompactItemize}


\doxysubsubsubsubsection{Detailed Description}
DMA FIFO direct mode. 



\label{doc-define-members}
\Hypertarget{group___d_m_a___f_i_f_o__direct__mode_doc-define-members}
\doxysubsubsubsubsection{Macro Definition Documentation}
\Hypertarget{group___d_m_a___f_i_f_o__direct__mode_gaec22b199f9da9214bf908d7edbcd83e8}\index{DMA FIFO direct mode@{DMA FIFO direct mode}!DMA\_FIFOMODE\_DISABLE@{DMA\_FIFOMODE\_DISABLE}}
\index{DMA\_FIFOMODE\_DISABLE@{DMA\_FIFOMODE\_DISABLE}!DMA FIFO direct mode@{DMA FIFO direct mode}}
\doxysubsubsubsubsubsection{\texorpdfstring{DMA\_FIFOMODE\_DISABLE}{DMA\_FIFOMODE\_DISABLE}}
{\footnotesize\ttfamily \label{group___d_m_a___f_i_f_o__direct__mode_gaec22b199f9da9214bf908d7edbcd83e8} 
\#define DMA\+\_\+\+FIFOMODE\+\_\+\+DISABLE~((uint32\+\_\+t)0x00000000U)}

FIFO mode disable \Hypertarget{group___d_m_a___f_i_f_o__direct__mode_ga18709570bed6b9112520701c482fbe4b}\index{DMA FIFO direct mode@{DMA FIFO direct mode}!DMA\_FIFOMODE\_ENABLE@{DMA\_FIFOMODE\_ENABLE}}
\index{DMA\_FIFOMODE\_ENABLE@{DMA\_FIFOMODE\_ENABLE}!DMA FIFO direct mode@{DMA FIFO direct mode}}
\doxysubsubsubsubsubsection{\texorpdfstring{DMA\_FIFOMODE\_ENABLE}{DMA\_FIFOMODE\_ENABLE}}
{\footnotesize\ttfamily \label{group___d_m_a___f_i_f_o__direct__mode_ga18709570bed6b9112520701c482fbe4b} 
\#define DMA\+\_\+\+FIFOMODE\+\_\+\+ENABLE~((uint32\+\_\+t)\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga89406bb954742665691c0ac2f8d95ec9}{DMA\+\_\+\+Sx\+FCR\+\_\+\+DMDIS}})}

FIFO mode enable 